;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
;
; (C) Copyright 2006 Marvell International Ltd.
; All Rights Reserved
;
;++
;
; Module Name:
;
;    oemaddrtab_cfg.inc
;
; Abstract:
;
;  This file is used to define g_oalAddressTable. This table is passed to
;  KernelStart to estabilish physical to virtual memory mapping. This table
;  is used also in IOMEM OAL module to map between physical and virtual
;  memory addresses via OALPAtoVA/OALVAtoPA functions.
;
; Environment:
;
; Revision History:
;
;--
;
; Copyright ?2002-2003 Intel Corp.
;
;-------------------------------------------------------------------------------
;

; Export Definition

        EXPORT  g_oalAddressTable[DATA]

;------------------------------------------------------------------------------
;
; TABLE FORMAT
;       cached address, physical address, size
;------------------------------------------------------------------------------

; *NOTE:  It is required that we provide a flat-map descriptor when enabling the MMU.  For eboot, you can simply insert a line
;   in the table below.  For the kernel, you cannot as it does not properly handle addresses < 0x80000000.  	    
ALIGN
g_oalAddressTable

    IF :DEF: BSP_DDR128MB
	DCD	0x80000000, 0xBC000000, 128      ; LITTLETON DDR SDRAM (128 MB).
    ELSE
	DCD	0x80000000, 0xBC000000, 64      ; LITTLETON DDR SDRAM (64 MB).
    ENDIF
	DCD	0x88000000, 0x40000000, 34	; MH:  Peripheral Group 1
	DCD	0x8B000000, 0x43000000, 1	; MH:  Caddo
	DCD	0x8B100000, 0x43100000, 1	; MH:  NAND Controller
	DCD	0x8B200000, 0x44000000, 1	; MH:  LCDC
	DCD	0x8B300000, 0x46000000, 1	; MH:  Px1 Group 1
	DCD	0x8B400000, 0x48100000, 1	; MH:  DMC
	DCD	0x8B500000, 0x4A000000, 1	; MH:  SMC
	DCD	0x8B600000, 0x4C000000, 1	; MH:  USBH 1.0
	DCD	0x8B700000, 0x50000000, 1	; MH:  Quick Capture
	DCD	0x8B800000, 0x54000000, 1	; MH:  2D
	DCD	0x8B900000, 0x54100000, 1	; MH:  USBH 2.0
	DCD	0x8BA00000, 0x58000000, 1	; MH:  IM CTL
	DCD	0x8BB00000, 0x5C000000, 1	; MH:  IM Array
	DCD	0x8BC00000, 0x20000000, 64	; MH:  PCMCIA IO (not on Littleton)
	DCD	0x8FC00000, 0x28000000, 64	; MH:  PCMCIA ATT (not on Littleton)
	DCD	0x93C00000, 0x2C000000, 63	; MH:  PCMCIA CMN (not on Littleton)

	DCD	0x97B00000, 0x14200000, 1	; MH:  Debug HEX LED (nCS3 high)
	DCD	0x97C00000, 0x10000000, 32	; LITTLETON:  nCS2, NOR
	DCD	0x99C00000, 0x30000000, 1	; LITTLETON:  nCS3 (low), LAN Controller
	DCD	0x9C000000, 0xBC000000, 4	; to avoid prefetch failure, 0xBC00_0000 must have same virtual/physical address.
	
        DCD     0x00000000, 0x00000000, 0       ; end of table

;------------------------------------------------------------------------------

        END
